Fabricating an integrated circuit, a chip, or a die or processing a carrier may include at least one etch process to generate the desired shape of a structure element. Applying an etch process, such as plasma etching or reactive plasma etching for example, may in face of many advantages have the problem that loading mechanisms (loading effects), e.g. micro-loading or aspect ratio dependent etching may occur. Thereby, a hole (or a recess) included in an integrated circuit on a carrier having a larger open area may finally have a larger depth than another hole (or another recess) having a smaller open area, despite using the very same etch process for both holes (or both recesses). Therefore, the distance between adjacent structure elements on a wafer and the dimensions of a structure element may influence the etch rate during an etch process.